The present invention relates to a surface emitting semiconductor laser typically used for optical interconnections, optical switch and optical information processing, and a process for producing such a laser.
Recently, there has been considerable activity in the development of optical interconnections directed toward dramatically improved transmission rates as means for transmitting information between logic circuit elements. Attention is attracted to a surface emitting semiconductor laser that enables light-emitting elements to be densely arranged in two dimensions as a parallel source. Such a laser is frequently called vertical cavity surface emitting laser diode (which will be hereinafter referred to as VCSEL simply). Pioneer researches in the VCSEL have been conducted by Ueki et al., “Single-Transverse-Mode 3.4-mW Emission of Oxide-Confined 780-nm VCSEL's”, IEEE PHOTONICS TECHNOLOGY LETTERS. VOL. 11, NO. 12, DECEMBER 1999, pp.1539–1541.
Referring to FIGS. 5A and 5B, a recent structure of the VCSEL has a resonator 702 that vertically extends from the horizontal surface of a semiconductor substrate 701. The resonator 702 has a mesa structure, and includes an active layer 703, a lower reflection mirror 704, an upper reflection mirror 705, and a spacer layer 706. The active layer 703 confines a carrier and results in light. Each of the mirrors 704 and 705 is made up of a plurality of semiconductor layers. The spacer layer 706 makes phase matching of the light emitted by the active layer 703 at the ends of the reflection mirrors 704 and 705. On the upper reflection mirror 705, provided are an upper contact layer 707, an upper electrode 708, an interlayer insulating film 710 and a lower electrode 709 in this order. The upper electrode 708 defines an aperture via which the laser beam is emitted. The interlayer insulating film 710 covers the sidewall and upper edge portions of the mesa structure.
Laser oscillation is conducted by confining the carrier and light in the horizontal direction in addition to the vertical direction. A confinement structure in the horizontal direction with respect to the substrate may be constructed by any of the following methods. The first method employs dry etching by which a boss (post or mesa) structure as thin as about ten and a few microns is formed. The second method is of oxidization type. A post structure having a diameter as large as tens of microns by dry etching and the property of an AlAs layer called control layer is partially changed into insulation by moisture vapor oxidation so that a restricted current path can be defined. The third method is of implantation type. The third method forms an insulating region by proton implantation and results in the restricted current path. At present, it is acknowledged that the oxide-confined VCSEL has a comparatively low threshold current and exhibits an excellent optical characteristic as a function of current. This is described in, for example, Journal of Solid State Physics and Applications Division, Vol. 5, No. 1, 1999, pp. 11. In FIGS. 5A and 5B, an oxide region in the AlAs layer 712 is indicated by a reference numeral 712A, and a non-oxide region therein is indicated by a reference numeral 712B. An aperture 713 is formed in the upper electrode 708 and the laser beam is emitted via the aperture 713. FIG. 5A and 5B differ from each other in that the semiconductor layer on which the interlayer film located on the bottom of the mesa structure is formed is a surface-oxidized layer 714 of a GaAs layer of the semiconductor substrate 701 or a surface-oxidized layer 715 of an AlGaAs layer that is part of the lower reflection mirror 704. The above difference results in a difference in the post height.
A description will now be given, with reference to FIGS. 6A through 6F, of steps of the process for producing the oxide type VCSEL until the interlayer insulating film is provided.
Referring to FIG. 6A, on an n-type GaAs semiconductor substrate 801, provided are an n-type GaAs buffer layer 802, a distributed Bragg reflector layer (DBR layer) 803, a λ (one wavelength) Al0.6Ga0.4As spacer layer 804, an AlAs layer 807, a DBR layer 808 and a p-type GaAs cap layer 809 in this order by MOCVD (Metalorganic Chemical Vapor Deposition). The DBR layer 803 is composed of 35 n-type Al0.3Ga0.7As/Al0.9Ga0.1As layers. The spacer layer 804 has two Al0.10Ga0.90As quantum well active layers 805, and three Al0.30Ga0.70As barrier layers 806. One of the two layers 805 is sandwiched between two of the barrier layers 806, and the other layer 805 is sandwiched between two of the layers 806. It is to be noted that FIG. 6A shows only one barrier layer 806, and the two remaining barrier layers 806 provided on the upper surface of the upper active layer 805 and the lower surface of the lower active layer 805 are omitted for the sake of simplicity. It may be said that the barrier layers 806 that are omitted from illustration are interposed between the active layers and the spacer layers. The DBR layer 808 is composed of 28 p-type Al0.3Ga0.7As/Al0.9Ga0.1As pairs. The cap layer 809 functions as a contact layer. The layers thus laminated form a VCSEL substrate.
Next, as shown in FIG. 6B, a resist pattern for forming a contact electrode on the p-type GaAs cap layer of the VCSEL substrate is formed by the conventional photolithograph process (PLP). Then, an electrode metal such as Cr/Au or Ti/Au is deposited. Subsequent liftoff of the resist results in contract electrodes 810.
Then, as shown in FIG. 6C, an insulating film such as a SiON or SiO2 film acting as a mask in dry etching is deposited in order to define the post or mesa structure. Then, the insulating film is etched by buffered hydrofluoric acid (BHF) wherein resist formed by the conventional PLP is used as the mask. Thereby, an insulating mask 811 is defined.
As shown in FIG. 6D, the wafer is dry-etched in a mixture gas of BCl3 and Cl2 with the mask pattern 811 of the insulating film. This results in a post structure 812 on the VCSEL substrate. The height of the post structure may be defined by the any of two ways of etching described below. The first way of etching progresses beyond the DBR layer 803 composed of 35 n-type Al0.3Ga0.7As/Al0.9Ga0.1As layers and reaches the GaAs substrate 701, as shown in FIG. 5A. The second way stops etching in the course of etching the DBR layer 803. As shown in FIG. 5A, when the GaAs substrate 801 as well as the DBR layer 803 are etched, the resultant post structure is too high to maintain the satisfactory accuracy in the post process. Particularly, there may be difficulty in production of a dense element array. With the above in mind, it is preferable that the height of the post structure is restricted so that etching is stopped in the course of etching the DBR layer 803.
Then, as shown in FIG. 6E, the VCSEL substrate on which the post structure 812 has been formed is oxidized in moisture vapor ambience at an anneal temperature of 350° C.–450° C. The AlAs layer 807 exposed to the sidewall of the post structure 812 is oxidized toward the center of the post structure 812 from the end thereof, so that an oxide region 813 dependent on the oxidizing time can be formed. The oxide region 813 is a porous insulating film, which serves as a current blocking layer for current confinement. A remaining AlAs region 814 that has not been oxidized (non-oxide region) defines a current path. The non-oxide region 814 has a refractive index different from that of the oxide region 813, and therefore acts as an aperture for controlling the horizontal mode of laser light.
Thereafter, as sown in FIG. 6F, the entire post structure is coated with a SiNex, SiO2 or SiOxNy film by CVD, so that an interlayer insulating film 815 can be formed. This is intended to reinforce the post structure because the oxidized region of the AlAs layer 807 is a porous thin film and is structurally weakened. Japanese Unexamined Patent Publication No. 11-340565, the applicant of which is the same as the assignee of the present application, discloses the use of an AlAs control layer (current confinement layer) that has an Al composition of 100%. The above publication proposes to reinforce the mesa structure by coating it with an interlayer insulating film in order to solve a problem such that the mesa structure after the oxidization process may be removed due to a post process of rapid annealing. Next, an electrode material is deposited, and is then annealed at about 400° C. in order to make the electrode ohmic.
However, the interlayer insulating film 815 may be released from the coated surface on the bottom of the mesa structure in annealing at about 400° C. for making the electrode ohmic. In some VCSEL substrates, the interlayer insulating film 815 may float above the coated surface or may be totally separated from the mesa structure. If the degree of separation is too bad, the interlayer insulating film 815 may go into pieces and may be scattered. The above reduces the number of normal VCSEL elements and degrades the reliability thereof. As a result, the yield of VCSEL elements may be degraded to tens to 50%.